The scheme works as follows, at receipt of a code combination (from 000 to 11 on an entrance coincidence (by means of schemes I is looked for) and on the corresponding exit tension of logical unit arrives. Inverters are required for transformation of the code combinations containing logical zero.
Further development of the schematic diagram of the SWITCHING ELEMENT is reduced to substitution of the developed library elements according to a function chart of this block. Memories on the schematic diagram of the block are presented in the form of separate elements. Development of the schematic diagram was conducted by means of the program of circuitry modeling, and all elements of this device are presented in the ANS standard the Schematic diagram of a switching element is submitted in figure 1
The schematic diagram of the SWITCHING ELEMENT is also under construction on the basis of a function chart, but in this case it is necessary to consider connection of the cells of memory which are a part of two RAMS (a memory of the address and information memorable devices.